1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a clock control circuit and a semiconductor integrated circuit using the same.
2. Related Art
Semiconductor integrated circuits with a high integration level and capable of operating at a high speed are increasingly in demand. Specifically, these high speed circuits include DLL (delay-locked loop) circuits to implement read operations in synchronization with external clock signals.
As is well known in the art, a DLL circuit is provided to control the output timing of a signal (for example, data, etc.), which is output by a semiconductor integrated circuit, in synchronization with the clock signal, which is input to the semiconductor integrated circuit. In detail, since timing delay occurs when the clock signal received by the semiconductor integrated circuit is used within the semiconductor integrated circuit, a DLL circuit is employed to control the timing delay and allow the clock signal used within the semiconductor integrated circuit to be synchronized with the clock signal received by the semiconductor integrated circuit.
An SDRAM (synchronous dynamic random access memory), for example, includes a DLL circuit to implement read operations in synchronization with external clock signals. As a consequence, the SDRAM is controlled in a read operation mode by the rising and falling clock signals generated by the DLL circuit, so that data can be output precisely in synchronization with the rising and falling edges of the external clocks signals. Meanwhile, the enable timing of output data is controlled so that a duty ratio can always be satisfied irrespective of a data pattern.
In general, in order to maintain the duty ratio between clock signals at 50:50, the rising and falling clock signals are controlled such that the rising edge of the rising clock signal and the falling edge of the falling clock signal cross at an intermediate point between a high level and a low level and the falling edge of the rising clock signal and the rising edge of the falling clock signal cross at the intermediate point between the high level and the low level. Therefore, when an output buffer is driven, as data is pulled up and pulled down depending upon the pattern of output data, an overlap of two signals occurs, and due to this fact, a PMOS transistor and an NMOS transistor in a pre-driver or an output buffer are simultaneously turned on and off, which serves as noise in the data output and can cause distortion and increase power consumption.